搜索资源列表
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
FPGA_FFT
- 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
alu
- verilog code for alu in RISC processor
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
verilog_design_a_simple_cpu
- 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
mmarm_EDACN
- 用FPGA实现ARM嵌入式处理器功能的Verilog源码及说明-FPGA with embedded ARM processor to achieve the functional descr iption of Verilog source code and
TrackingPresentation_jon
- presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board wi
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
AMBAaxi
- amba with arm processor descr iption and use
mips
- in verilog 8bit mips processor
grlib-tmtc-1.0.18.tar
- Zipped LEON3 processor VHDL core.
processor
- 文件中包含一个简单MIIPS CPU的Verilog源代码-File contains a simple MIIPS CPU in Verilog source code
fft
- vhdl code and verilog code for an 128 point fft processor which has to be executed in xlinx software as needed for course project
SAP-processor-with-Test-Bench-working
- SAP processor in verilog with test bench complete and working
cpu
- 用verilog实现的一个32位RISC处理器，能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
VERILOG-DESIGN-OF-INPUTOUTPUT-PROCESSOR
- VERILOG DESIGN OF INPUTOUTPUT PROCESSOR WITH BUILT-IN-SELF-TEST GOH KENG
MIPS-processor-Verilog-code
- 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instruct
Verilog-Source
- mips 处理器verilog文件， 适合做处理器开发的人员参考-the mips processor verilog file suitable processor development reference
processor
- 通过verilog语言编程实现简单的微处理器，实现简单的加减和复制功能。-Through the verilog language programming simple microprocessor, simple addition and subtraction, and copy functions.
verilog-FAQ
- Low power SRAMs have become a critical component of many VLSI chips. This is true for microprocessors, where on-chip cache sizes are growing with each generation to bridge the increasing divergence in the speeds of the processor and main memory. Simu